How AMD 3D V-Cache can improve Ryzen efficiency by as much as 25 %

AMD stated Monday night at Computex 2021 that it has advanced its chiplet structure into 3D chiplets, particularly what it calls 3D V-Cache know-how. By itself, the know-how guarantees efficiency positive aspects for its Ryzen and Epyc processors that may contact 25 %.

AMD has made “nice progress” on its 3D chiplet know-how, and may debut it in its “highest-end merchandise” by the tip of 2021, AMD chief government Dr. Lisa Su stated throughout a Computex keynote tackle.3D V-Cache permits AMD to take a Ryzen 5000 cell processor and join a 64MB SRAM cache instantly on high of it.

Su confirmed off a Ryzen 9 5900X, AMD’s quickest gaming CPU, after which in contrast it to a prototype 5900X with 3D V-Cache connected to it. In Xbox Recreation Studios’ Gears 5, body charges improved by 12 %. In different video games, additionally utilizing an identically clocked 5900X, efficiency elevated four to 25 %, for a median of 14 %, Su stated.

amd computex 2021 3d v cache gaming fps 2 YouTube / AMD

AMD’s Dr. Lisa Su offered benchmarks exhibiting how the prototype 3D V-Cache can dramatically enhance gaming efficiency.

Stacked chips sound like the longer term

This will likely all sound acquainted. In 2018, Intel started exhibiting off how its Foveros know-how allowed for stacking its CPU logic on high of each other. That allowed Intel to create the short-lived Lakefield processor, but additionally the upcoming, higher-performing Alder Lake chip, which Intel displayed at Computex in each desktop and cell variations. 

amd computex 2021 3d v cache diagram better large YouTube / AMD

AMD CEO Dr. Lisa Su explains 3D V-Cache in her Computex presentation.

In response to Tirias Analysis analyst Kevin Krewell, nevertheless, AMD’s implementation of 3D stacking know-how is completely different. AMD is utilizing through-silicon through know-how from TSMC, its foundry companion, just like the know-how utilized by reminiscence makers to stack DRAM and NAND flash on high of each other. It has higher energy and bandwidth traits than Foveros, but it surely’s unknown how effectively it may be manufactured.

“AMD is utilizing the tech to get an additional ~12 % efficiency increase for its CPUs by including extra L3 cache,” Krewell stated through on the spot message. “This know-how may also be utilized in EPYC servers.”

Putting a big cache instantly adjoining to the CPU can have important efficiency benefits. Processors have to ask for directions, and storing them in an simply accessible cache—versus in search of them out in system reminiscence—could be a straightforward solution to improve system efficiency. However baking that cache into the processor die introduces extra alternative for chip defects. In a worst-case situation, the whole chip might be rendered ineffective.

Including the cache as a separate die after which stacking it saves house and value, whereas nonetheless sustaining the bandwidth benefit and including gobs of obtainable cache. For instance, Su stated its prototype soldered SRAM to every AMD CCD, for a complete of 192MB of SRAM cache. The out there level-Three cache on as we speak’s 5900X is simply 64MB, or a 3rd of the 3D V-Cache prototype.

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